Simulation has long been an essential step in the design and manufacture of microelectronic circuits and systems. Present day Ultra-Large Scale Integration (ULSI) devices may include hundreds of thousands or millions of active electronic devices on an integrated circuit chip, which are interconnected on the chip to perform a particular function. The large capital investment required to fabricate microelectronic devices and the difficulty in reworking microelectronic devices which do not operate as planned, have produced the need to simulate circuit performance before manufacture.
Accordingly, many simulators have been developed and marketed. One widely used circuit simulator is a program which was developed at the Electronics Research Laboratory of the University of California, Berkeley, known as SPICE. A popular version of SPICE (SPICE 2) is described in "SPICE Version 2G.1 User's Guide" Berkeley: University of California, Department of Electrical Engineering and computer Science, 1980 by Vladimirescu et al. Circuit simulators have also been the subject of patent protection because they are an integral part of the design and fabrication of microelectronic devices. Recently issued patents concerning circuit simulators are U.S. Pat. No. 4,918,643 to Wong entitled Method and Apparatus for Substantially Improving the Throughput of Circuit Simulators; U.S. Pat. No. 5,047,971 to Horwitz entitled Circuit Simulation; and U.S. Pat. No. 5,051,911 to Kimura et al. entitled Apparatus for Effecting Simulation of a Logic Circuit and Method for Producing a Semiconductor Device Using the Simulation Approach.
Circuit simulators are typically software based, and are designed to accept a description of the circuit which defines the circuit topology and element values. Each element in the circuit is typically specified by an element line containing the element name, connected nodes, and electrical parameter values. Simulators typically simulate circuits which contain passive devices such as resistors, capacitors, inductors and mutual inductors, voltage and current sources, and active devices such as diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET) and metal oxide semiconductor field effect transistors (MOSFET). The simulator can typically be configured to perform DC analysis, AC small signal analysis and transient analysis.
As the feature sizes of integrated circuits continue to shrink, and operating speeds increase, the characterization of the parasitic effects associated with the interconnect paths among the active devices becomes more critical and more difficult. In the past, the effect of interconnects could simply be disregarded when simulating the operation of an integrated circuit, because the active circuit elements dominated the simulation in terms of delay. However, as the feature sizes of integrated circuits continue to shrink, the metal resistance per unit length tends to increase and the switching speeds tend to increase. In addition, the close proximity of metal lines makes the component cross-talk capacitance larger. Even inductance effects, which are evident for boards and multichip modules which comprise microelectronic systems, may also be important for modeling the integrated circuit packaging or chip-to-package interface. Accordingly, a complete circuit simulation of an integrated circuit must now account for the resistive, inductive and capacitive effects of the interconnect paths in addition to simulating the effect of the active devices on the integrated circuit.
It will be understood by those having skill in the art that a conventional circuit simulator, such as SPICE, could be used for a complete characterization of an integrated circuit, including the active devices and the interconnect paths. However, because of the large numbers of circuit elements involved, a complete simulation becomes extremely time consuming and may exceed the storage capabilities of the processing system on which the simulation is run.
A major improvement in the simulation of interconnects is described in a publication by Lawrence T. Pillage and Ronald A. Rohrer, entitled Asymptotic Waveform Evaluation for Timing Analysis, IEEE Transactions on Computer-Aided Design, Vol. 9, No. 4, April 1990, pp. 352-366, the disclosure of which is hereby incorporated herein by reference. Described is an Asymptotic Waveform Evaluation (AWE) methodology to provide a generalized approach to linear resistor-inductor-capacitor (RLC) circuit response approximations. AWE is a general method for computing any number of moments for any linear circuit. Using the method, a qth order approximation to the actual circuit response can be obtained by computing 2 q moments of the circuit and matching these moments to the circuit's impulse response. The moments, in their simplest interpretation, represent the coefficients of the s-terms in the Taylor series expansion of the homogenous circuit response. Once the desired number of moments are found, they may be mapped to the dominant poles and corresponding residues. Once the poles and residues of the approximate response are found, the time domain response of the interconnect circuit may be determined.
In the AWE technique, moments of a circuit may be generated by successively solving an equivalent DC circuit with all capacitors replaced by current sources and all inductors replaced by voltage sources. The resulting voltages across the capacitors and currents through the inductors comprise one generation of circuit moments. Initially, all capacitor-current sources and inductor-voltage sources are set to zero, and independent voltage and current sources of the actual circuit are set to their final values. For subsequent moment generations, each capacitor-current source is set to the product of its capacitance and its previous moment, while each inductor-voltage source is set to the product of its inductance and its previous moment. This process may be continued until the desired number of moments are calculated.
It has been shown that, for large numbers of interconnects, AWE can provide a hundredfold speed increase compared to a conventional SPICE circuit simulation. However, notwithstanding the above described improvements, further improvements in efficiency are necessary to accommodate higher density integrated circuits. Moreover, it is known that moment matching techniques may yield unstable models having positive time constants (positive poles) for linear, passive (stable) circuits. This instability can be mainly attributed to two phenomena: (1) the extreme sensitivity of the moment values to numerical noise, and (2) the zero locations that characterize the high frequencies associated with impulse- and step-response approximations. The number of matched moments may be increased to avoid this instability. However, the result may be even more susceptible to numerical noise or may also be inherently unstable.